Reference is made to an article by Okamura et al., at page 18 in the February 1990, Volume 25, No. 1 issue of the IEEE Journal of Solid State Circuits entitled "Decoded-Source Sense Amplifier for High-Density DRAM's", for a description of a sensing amplifier system of which the present invention is an improvement. The teachings of this article are incorporated herein by reference. Such an amplifier is hereinafter referred to as DSSA and is illustrated by way of example in FIG. 1 herein. Its purpose is to produce signals in a pair of lines having a voltage differential indicative of whether the voltage on a data storage capacitor associated with one of the said lines represents a digital 0 or a digital 1. Each DSSA senses one of typically 256 or more cells arranged in a single column of a memory.
FIG. 1, which illustrates the DSSA of the above article, includes data storage capacitors 2 and 4 which are connected to bit lines 6 and 8, respectively through select transistors 46 and 56. Only an N channel sense amplifier is shown (typically including NMOS transistors) in the interest of simplicity, but as is known by those skilled in the art, P channel circuitry is typically also required. During a writing process, not described, the capacitors 2 and 4 are charged to voltages representing logic 1 or logic 0 relative to the voltage between lines 6 and 8. Field effect transistors (FET's) 10 and 12 are connected with their source/drain paths in series with the bit lines 6 and 8, respectively, and a voltage V.sub.cc from a point 14 is applied to their commonly connected gate electrodes 16 and 18, for providing isolating resistances relative to respective bit lines 6, 8. Cross-coupled FET's 20 and 22 (providing an N-channel flip flop) are connected with their source/drain paths respectively in series with the source/drain paths of the FET's 10 and 12. A drain electrode 24 of the FET 20 is connected to a source electrode 26 of the transistor 10 and to a gate electrode 27 of the FET 22. A drain electrode 28 of the FET 22 is connected to a source electrode 30 of the FET 12 and to a gate electrode 31 of the FET 20. Source electrodes 32 and 34 of the FET's 20 and 22, respectively, are connected to a drain electrode 36 of a FET 38, and its source electrode 40 is connected to a bus SAN (sense amplifier driving node). A gate electrode 42 of the FET 38 is connected to a source of voltage V.sub.cc so that the resulting impedance of the channel of FET 38 becomes a barrier or isolating resistive impedance. A FET 39 (Q.sub.san in the above article) is connected with its channel or main current path between the bus SAN and ground VSS. A resistor 44 represents the distributed resistance of the bus SAN. Many other cells like that just described are coupled to the bus SAN in the same manner.
When actuated in a manner to be described, the flip flop 20, 22 assumes a state depending on the voltage stored on the selected capacitor, 2 or 4, in this example. The voltage at the drain electrode 24 of the FET 20 is coupled to an external bit line 45 via the channel of a FET 46 having a source electrode 48, and a drain electrode 50. A gate electrode 52 of FET 46 is connected to a source of CSL (column select line) signals 72. The voltage at the drain electrode 28 of the FET 22 is coupled to an external bit line 54 via the channel of a FET 56 having a source electrode 58, and a drain electrode 60. A gate electrode 62 of FET 56 is connected to the source of CSL signals 72.
The drain electrode 64 of a FET 66 is connected to the source electrodes 32 and 34 of the FET's 20 and 22, and its source electrode 68 is connected to a point 70 that is at a decoded ground potential DSETN. This decoded ground DSETN differs from that to which the switch 39 (Q.sub.san) is connected in that it is an isolated source of reference potential having much less noise associated therewith.
In a high density DRAM, many more cells are read (restored) than are brought out to off chip drivers. Each storage cell which is read is connected to a DSSA which is activated as described in the above-referenced article. The bit lines 6 and 8 are precharged to a voltage Vdd/2, and the external bit lines 45 and 54 are precharged to a voltage near Vdd. Methods and apparatus for accomplishing the precharging of bit lines 6, 8, 45, and 54 are known in the art. The DSSAs which are sensing cells which are only to be restored are activated by the SAN signal which moves from a Vdd/2 precharge voltage to ground through the turning on of FET 39. When the storage cell information is to be brought to an off-chip-driver, a column selection signal CSL is applied by CSL signal source 72 to a lead 73 connected to a gate electrode 74 of the FET 66 for that cell, and to the gate electrodes 52, 62 of the FET's 46 and 56.
The sense amplifier system DSSA just described attains an advantage over the conventional system by use of the FET's 66 and 38 which allow the DSSA's containing data which are to be driven off-chip (those selected by a CSL signal) to be set faster by use of a `clean ground`. When made conductive by application of the column select signal CSL to its gate electrode 74, FET 66 connects the source electrodes 32 and 34 of FET's 20 and 22 to the "quiet" decoded ground DSETN at terminal 70, causing FET's 20 and 22 to become firmly and quickly latched. The majority of DSSA's, which are sensing data not read out to off chip drivers, will all set at a slower rate through the "noisy" setbus which is pulled low via FET 39.
FET 38 is of help in the case of weak columns because their weaker preamplified current causes less voltage drop across the impedance of their FET corresponding to FET 38 than the greater preamplified currents of a normal cell. Weak column action is discussed in the above-referenced article.
In order to maximize the speed of the transfer of information from the bit lines 6 and 8 to the external bit lines 45 and 54, the CSL signal supplied by the source 72 rises rapidly from decoded ground DSETN to V.sub.DD as indicated by the graph line 76 of FIG. 2. Operation is satisfactory as long as the FET's 46 and 56 are nearly perfectly matched, but the signals developed on the external bit lines 45 and 54 are unreliable if the FET's 46 and 56 are not closely matched.